Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...
EDN

Reducing switching power with intelligent clock gating

Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a ...
EDN

Power tool taps clock gating

Claiming breakthrough technology in IC power optimization, Calypto Design Systems Inc. (Santa Clara, Calif.) this week will announce PowerPro CG, a tool that automatically adds clock-gating logic to ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...