EDN

Recycle RTL test benches to verify Transaction-Level IP Models

System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
Semiconductor Engineering

GNN-Based Pre-Silicon Power Side-Channel Analysis Framework At RTL Level

A technical paper titled “SCAR: Power Side-Channel Analysis at RTL-Level” was published by researchers at University of Texas at Dallas, Technology Innovation Institute and University of Illinois ...
EDN

RTL, gate-level tools fill out floor plan flow

SAN MATEO, Calif. — IC floor-planning tool startup InTime Software Inc. will release an RTL floor planner and a gate-level floor planner to complement its architectural-level floor planner at the ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...