Business Wire

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

SANTA CLARA, Calif.--(BUSINESS WIRE)--Further expanding SiFive’s lead in RISC-V AI IP, the company today launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products ...
EDN

RISC-V IP expands AI capabilities at the edge

SiFive’s Intelligence Gen 2 RISC-V IP portfolio combines scalar, vector, and matrix compute to accelerate AI workloads. The Gen 2 lineup includes the new X160 and X180, alongside the upgraded X280, ...
Network World

What are TPUs? Your guide to tensor processing units and AI acceleration

TPUs are Google’s specialized ASICs built exclusively for accelerating tensor-heavy matrix multiplication used in deep learning models. TPUs use vast parallelism and matrix multiply units (MXUs) to ...
Morningstar

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center

SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center New X100 Series Joins Upgraded X200, X300 and XM IP to Address Growing ...