At the beginning of my career in semiconductor equipment, the backside of the wafer was a source of anxiety. In one memorable instance in my early career, several wafers flew off a robot blade during ...

Imec has presented an experimental demonstration of a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs).

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower ...

KLA-Tencor Corp. hopes to open a new market for wafer backside inspection with the introduction of an automated wafer backside inspection module today for its Surfscan 300mm-defect inspection tool.

Through the looking glass: Many advances in semiconductor technology hinge on reducing package sizes while incorporating added functionality and more efficient power delivery methods. Present methods ...

During lapping, a spinning abrasive surface is used to thin wafers from the backside. As the process progresses, precise feedback is required to monitor the amount of material removed and determine ...

Rudolph Technologies has announced the first shipment of its all-surface macro-defect detection system to a US-based manufacturer of flash memories. The system, which will be installed in a ...