IEEE

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Abstract: Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology ...
IEEE

Depth Dependence of Neutron-Induced Errors in 3-D NAND Floating Gate Cells

Abstract: The sensitivity of vertical-channel 3-D NAND Flash memories to wide-energy spectrum neutrons is investigated as a function of cell depth in the pillars. Errors are found to be less numerous ...