A RISC-V CPU simulator implemented in Python using assassyn. To use this project, you should configure assassyn environment first. RISC-V-CPU/ ├── cpu/ # CPU core modules │ ├── __init__.py # Package ...
This repository is the submission from the Speech Squad team for the MTC-AIC 2 challenge. It contains the code for our experiments in training an Automatic Speech Recognition (ASR) model for the ...
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